中国大学MOOC: 下面是一个计数器模块的代码，哪一种说法不正确？module counter (qout, reset, clk);out

1.下面是一个计数器模块的代码，哪一种说法不正确？module counter (qout, reset, clk);output [3:0] qout;input clk, reset;reg [3:0] qout;always @ (posedge clk) begin if (reset) qout<=0; // else qout<=qout+1; // endendmodule 选项： A、该计数器是十六进制的 B、具有异步置0功能，而且是十进制的计数器 C、这是一个4位计数器 D、端口reset是同步置0的

2.中国大学MOOC: 以下Verilog HDL代码描述的是什么电路？module sr ( input wire clk,si,ld,reset,en, input wire [7:0]d, output reg [7:0]q ); always@(posedge clk, negedge reset) begin if(!reset) q <= 8b0000_0000; else begin if(en) q <= {q[6:0],si}; if(ld) q <= d; end end endmodule

3.【单选题】某设计的VerilogHDL程序如下,该设计描述的计数器的模是() module my_counter(input reset,clk,output reg[3:0] out); always@(posedge clk) Begin if(reset) out=0; else out=out+1; end endmodule 选项： A、4 B、8 C、16 D、32

4.以下代码描述的是:( ).module count(out,data,load,reset,clk);output[7:0] out; input[7:0] data;input load,clk,reset; reg[7:0] out;always @(posedge clk) begin if(!reset) out=8'h00; else if(load) out=data; else out=out+1; endendmodule

5.以下Verilog HDL代码描述的是什么电路？module sr ( input wire clk,si,ld,reset,en, input wire [7:0]d, output reg [7:0]q ); always@(posedge clk, negedge reset) begin if(!reset) q <= 8'b0000_0000; else begin if(en) q <= {q[6:0],si}; if(ld) q <= d; end end endmodule 选项： A、加法器 B、乘法器 C、移位寄存器 D、触发器

6.智慧职教: module dff_2（data,clk,reset,q); input data,clk,reset; output q; reg q; always@(posedge clk or negedge reset) begin if(reset==1’b0) q<=1’b0; else q <= data; end endmodule

7.以下Verilog HDL代码描述的是什么电路？module sr ( input wire clk,si,ld,reset,en, input wire [7:0]d, output reg [7:0]q ); always@(posedge clk, negedge reset) begin if(!reset) q <= 8'b0000_0000; else begin if(en) q <= {q[6:0],si}; if(ld) q <= d; end end endmodule 选项： A、加法器 B、乘法器 C、计算器 D、移位寄存器

8.中国大学MOOC: 以下代码描述触发器，请在空格中填写正确的数值module dff_sync_reset ( data , // Data Input clk , // Clock Input reset , // Reset input q // Q output ); //-----------Input Ports--------------- input data, clk, reset ; //-----------Output Ports--------------- output q; //------------Internal Variables-------- reg q; //-------------Code Starts Here--------- always @ ( posedge clk) if (~reset) begin q <= 1b ; end else begin q <= data; end endmodule

9.选出右移移位寄存器选项： A:module Shifter ( input Dsi, input CLK, output reg [3:0] Q); always@(posedeg clk) begin Q[3]<= Dsi; Q[2]<=Q[3]; Q[1]<=Q[2]; Q[0]<=Q[1];end endmodule; B:module Shifter ( input Dsi, input CLK, output reg [3:0] Q); always@(posedeg clk) begin Q[3]<=Q[2]; Q[2]<=Q[1]; Q[1]<=Q[0]; Q[0]<=Dsi; end endmodule; C:module Shifter ( input Dsi, input CLK, output reg [0:3] Q); always@(posedeg clk) begin Q[0]<= Dsi; Q[1]<=Q[0]; Q[2]<=Q[1]; Q[3]<=Q[2]; end endmodule; D:module Shifter ( input Dsi, input CLK, output reg [0:3] Q); always@(posedeg clk) Q[0:3]<={ Dsi,Q[0:2]};endmodule; E:module Shifter ( input Dsi, input CLK, output reg [0:3] Q); always@(posedeg clk) Q[0:3]<={Q[1:3],Dsi};endmodule; F:module Shifter (input Dsi, input [3:0] In, input CLK, output reg [3:0] Q); always@(posedeg clk) if(Load) Q<= In; else Q<={Dsi,Q[3:1]};endmodule; G:module Shifter (input Dsi, input CLK,reset, output reg [3:0] Q); always@(posedge clk or posedge reset) if(reset) Q<= 4'b1000;else Q<={Q[2:0],Q[3]}; end module

10.以下程序描述的电路结构,包含哪些元件？module test8(CLK,D,Q,RESET,EN,SET);input CLK,D,RESET,EN,SET;output Q;reg Q;wire PRE;assign PRE=SET & RESET;always@(posedge CLK or negedge RESET or posedge SET)begin if (!RESET) Q<=0;else if (SET) Q<=1;else if (EN) Q<=D;endendmodule选项： A:锁存器; B:D触发器; C:与门; D:或门

11.中国大学MOOC: 根据程序描述的逻辑功能，下列说法正确的有module Learn7_1(clk,CLR,LD,out); input clk,CLR,LD; output reg[3:0] out; always@(posedge clk or negedge CLR) begin if(!CLR) out<=0; else if(!LD) out<=15; else out<=out+1; endendmodule

12.以下程序描述的电路结构,包含哪些元件？module test8(CLK,D,Q,RESET,EN,SET);input CLK,D,RESET,EN,SET;output Q;reg Q;wire PRE;assign PRE=SET & RESET;always@(posedge CLK or negedge RESET or posedge SET)begin if (!RESET) Q<=0;else if (SET) Q<=1;else if (EN) Q<=D;endendmodule 选项： A、锁存器 B、D触发器 C、与门 D、或门

13.下面是一个D触发器的模块。阅读后指出，哪一种说法不正确？module mydff (clk, reset, load, d, q); input clk, d, reset, load; output q; reg q; always @ (posedge clk or posedge reset or posedge load) begin if (reset==1) // q<=0; else if (load==1) // q<=1; else q<=d; endendmodule 选项： A、该触发器具有异步端口reset和load； B、可以异步置0，可以异步置1 C、该触发器是下降沿触发 D、该触发器是上升沿触发

14.4位二进制加法计数器module count4(out,reset,clk);input reset,clk; output reg[3:0] out;A、lways @(posedge clk)B、eginC、if(reset) out<=0; //同步复位D、lse out<=out 1; //计数E、ndF、ndmodule

15.已知状态转移图如下：

请在下划线处填写正确的代码：module reduce (clk, reset, in, out); input clk, reset, in; output out; parameter S0 = 2’b00; parameter S1 = 2’b01; parameter S2 = 2’b10; reg out; reg [1:0] state; reg [1:0] next_state; always @(posedge clk) if (reset) state = S0; e lse state = next_state;always @(in or state) case (state) ………… S1: begin if (in) next_state = S2; else next_state = ; end …………

16.已知状态转移图如下：

请在下划线处填写正确的代码：module reduce (clk, reset, in, out);input clk, reset, in;output out;parameter S0 = 2’b00;parameter S1 = 2’b01;parameter S2 = 2’b10;reg out; reg [1:0] state;reg [1:0] next_state;always @(posedge clk) if (reset) state = S0; e lse state = next_state;always @(in or state) case (state)………… S1: begin if (in) next_state = S2; else next_state = ; end…………

17.module SHFT1(CLK,LOAD,DIN,QB); output QB; input CLK,LOAD; input[7:0] DIN; reg[7:0] REG8; always @(posedge CLK ) if (LOAD) REG8<=DIN ; else ____<=REG8[7:1]; assign QB = REG8[0] ; endmodule空格处应该填入：选项： A、LOAD B、DIN C、QB D、REG8[6:0]

18.根据程序描述的逻辑功能，下列说法正确的有： module Learn7_1(clk,CLR,LD,out); input clk,CLR,LD,data; output reg[3:0] out; always@(posedge clk or negedge CLR) begin if(!CLR) out<=0; else if(!LD) out<=data; else out<=out+1; end endmodule

19.阅读下面代码，该移位寄存器的输入、输出方式属于（）。module shift_reg(din,clk,clr,q); input din,clk,clr;output reg [3:0] q;always@(posedge clk or negedge clr)begin if(clr==1'b0) q<;=4'b0000; else begin q<;={q[2:0],din}; endendmodule 选项： A、串行输入串行输出 B、串行输入并行输出 C、并行输入串行输出 D、并行输入并行输出

20.选出具有使能控制的触发器或寄存器选项： A:module D_ff ( input D,CLK,En, output reg Q ); always@(posedge CLK) begin if (En) Q <= D; end endmodule; B:module D_ff ( input D,CLK,En, output reg Q ); always@(posedge CLK or posedge En) begin if (En) Q <=0; else Q =D; endendmodule; C:module D_ff ( input D,CLK, output reg Q ); always@(posedge CLK) begin Q <= D; end endmodule; D:module D_ff ( input D,CLK,En, output reg Q ); wire gateclk; assign gateclk=(En&CLK); always@(posedge GATECLK) begin if (En) Q < =D; end endmodule; E:module D_ff ( input CLK,load, input [3:0] D, output reg [3:0] Q ); always@(posedeg CLK) begin if (load) Q <= D; end endmodule

21.选出具有使能控制的触发器或寄存器选项： A:module D_ff ( input D,CLK,En, output reg Q ); always@(posedge CLK) begin if (En) Q <= D; end endmodule; B:module D_ff ( input D,CLK,En, output reg Q ); always@(posedge CLK or posedge En) begin if (En) Q <=0; else Q =D; endendmodule; C:module D_ff ( input D,CLK, output reg Q ); always@(posedge CLK) begin Q <= D; end endmodule; D:module D_ff ( input D,CLK,En, output reg Q ); wire gateclk; assign gateclk=(En&CLK); always@(posedge GATECLK) begin if (En) Q < =D; end endmodule; E:module D_ff ( input CLK,load, input [3:0] D, output reg [3:0] Q ); always@(posedeg CLK) begin if (load) Q <= D; end endmodule

22.选出正确的带复位控制的触发器选项： A:module D_FF ( input D,Clock,reset, output reg Q); always@(Posedge Clock or reset) if ( reset==1) Q <=0; else Q <=D; endmodule; B:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or posedge reset) if ( reset==1) Q <=0; else Q <=D; endmodule; C:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or negedge reset) if ( reset==1) Q <=0; else Q <=D; endmodule; D:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or posedeg reset) if ( reset==0) Q <=0; else Q <=D; endmodule; E:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or reset) if ( reset==1) Q <=0; else Q <=D; endmodule; F:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or reset) if ( reset==0) Q <=0; else Q <=D; endmodule; G:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock) if ( reset==1) Q <=0; else Q <=D; endmodule

中国大学MOOC: 下面是一个计数器模块的代码，哪一种说法不正确？module counter (qout, reset, clk);output [3:0] qout;input clk, reset;reg [3:0] qout;always @ (posedge clk) begin if (reset) qout<=0; // else qout<=qout+1; // endendmodule

中国大学MOO
C: 下面是一个计数器模块的代码，哪一种说法不正确？module counter (qout, reset, clk);output [3:0] qout;input clk, reset;reg [3:0] qout;always @ (posedge clk) begin if (reset) qout<=0; // else qout<=qout+1; // endendmodule