选出具有使能控制的触发器或寄存器
选项：

A:module D_ff ( input D,CLK,En, output reg Q ); always@(posedge CLK) begin if (En) Q <= D; end endmodule;
B:module D_ff ( input D,CLK,En, output reg Q ); always@(posedge CLK or posedge En) begin if (En) Q <=0; else Q =D; endendmodule;
C:module D_ff ( input D,CLK, output reg Q ); always@(posedge CLK) begin Q <= D; end endmodule;
D:module D_ff ( input D,CLK,En, output reg Q ); wire gateclk; assign gateclk=(En&CLK); always@(posedge GATECLK) begin if (En) Q < =D; end endmodule;
E:module D_ff ( input CLK,load, input [3:0] D, output reg [3:0] Q ); always@(posedeg CLK) begin if (load) Q <= D; end endmodule