已知状态转移图如下：<img src='https://fb.fbstatic.cn/api/ape-images/1802d4027583

请在下划线处填写正确的代码：module reduce (clk, reset, in, out);input clk, reset, in;output out;parameter S0 = 2’b00;parameter S1 = 2’b01;parameter S2 = 2’b10;reg out; reg [1:0] state;reg [1:0] next_state;always @(posedge clk) if (reset) state = S0; e lse state = next_state;always @(in or state) case (state)………… S1: begin if (in) next_state = S2; else next_state = ; end…………

2.选出摩尔型状态机选项： A:module fsm(input clk,acc,brake,reset,output [1:0] speed );reg [1:0] state;reg [1:0] next_state;localparam STOP=2'b00;localparam LOW=2'b01;localparam MEDIUM=2'b10;localparam HIGH =2'b11;//状态转换always@(posedge clk or posedeg reset)if(reset) state=STOP;elsestate=next_state;//次态计算always@(*)case(state)STOP:if (acc && !brake) next_state=LOW;else next_state=STOP;LOW:if (brake) next_state=STOP;else if (acc) next_state=MEDIUM;else next_state=LOW;MEDIUM:if (brake) next_state=LOW;else if (acc) next_state=HIGH;else next_state=MEDIUM;HIGH:if (brake) next_state=MEDIUM;else next_state=HIGH;endcase//输出逻辑assign speed=state;endmodule; B:module fsm(input clk,acc,brake,reset,input easy,output [1:0] speed );reg [1:0] state;reg [1:0] next_state;localparam STOP=2'b00;localparam LOW=2'b01;localparam MEDIUM=2'b10;localparam HIGH =2'b11;//状态转换always@(posedge clk or posedeg reset)if(reset) state=STOP;elsestate=next_state;//次态计算always@(*)case(state)STOP:if (acc && !brake) next_state=LOW;else next_state=STOP;LOW:if (brake) next_state=STOP;else if (acc) next_state=MEDIUM;else next_state=LOW;MEDIUM:if (brake) next_state=LOW;else if (acc) next_state=HIGH;else next_state=MEDIUM;HIGH:if (brake) next_state=MEDIUM;else next_state=HIGH;endcase//输出逻辑assign speed=easy ? 2'b01:state;endmodule; C:module fsm(input clk,acc,brake,reset,output [1:0] speed );enum bit [3:0] {STOP=4'b0001,LOW =4'b0010,MEDIUM=4'b0100,HIGH=4'b1000,}state,next_state;always@(posedge clk or posedeg reset)if(reset) state=STOP;elsestate=next_state;always@(*)case(state)STOP:speed=2'b00;if (acc && !brake) next_state=LOW;else next_state=STOP;LOW:speed=2'b01;if (brake) next_state=STOP;else if (acc) next_state=MEDIUM;else next_state=LOW;MEDIUM:speed=2'b10;if (brake) next_state=LOW;else if (acc) next_state=HIGH;else next_state=MEDIUM;HIGH:speed=2'b110;if (brake) next_state=MEDIUM;else next_state=HIGH;endcaseendmodule; D:module fsm(input clk,acc,brake,reset,output [1:0] speed );reg [1:0] state;localparam STOP=2'b00;localparam LOW=2'b01;localparam MEDIUM=2'b10;localparam HIGH =2'b11;assign speed=state;always@(posedge clk)case(state)STOP:if (acc && !brake) state=LOW;LOW:if (brake)state=STOP;else if (acc) state=MEDIUM;MEDIUM:if (brake)state=LOW;else if (acc)state=HIGH;HIGH:if (brake) state=MEDIUM;elsestate=HIGH;endcaseendmodule

3.下列Moore型状态机采用Verilog语言主控时序部分正确的是：选项： A、always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B、always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C、always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D、always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;

4.阅读下列代码，关于这段代码说法正确的是（）。module fsm_example ( clk, rst_n, datain, result);input clk，rst_n;input datain;output reg result;parameter IDLE = 2'b00;parameter S0 = 2'b01;parameter S1 = 2'b10;reg [1:0] curr_state,reg [1:0] next_state; always@(posedge clk or negedge rst_n) // 第一段begin if (~rst_n) curr_state <= IDLE; else curr_state <= next_state;end always@(*) // 第二段begin case (curr_state) IDLE : if (datain) next_state = S0; else next_state = IDLE; S0 : if (datain) next_state = S1; else next_state = IDLE; S1 : if (datain） next_state = S1; else next_state = IDLE; default : next_state = IDLE; endcaseend always@(*) // 第三段begin case (curr_state) IDLE : result = 1'b0; S0 : result = 1'b0; S1 : result = 1'b1; default : result = 1'b0; endcaseendendmodule 选项： A、这段代码中定义了3个状态：IDLE、S0、S1 B、用于序列检测，当连续输入三个clk周期的高电平时，输出result为高电平 C、第一个always语句块将下一个状态逻辑产生的状态存入curr_state D、第二、三个always语句块均是组合逻辑，前者根据输入和当前状态，产生next_state，后者根据当前状态产生输出

5.以下是一个摩尔型状态机module fsm(input clk,acc,brake,reset,input easy,output [1:0] speed );reg [1:0] state;reg [1:0] next_state;localparam STOP=2'b00;localparam LOW=2'b01;localparam MEDIUM=2'b10;localparam HIGH =2'b11;//状态转换always@(posedge clk or posedeg reset)if(reset) state=STOP;elsestate=next_state;//次态计算always@(*)case(state)STOP:if (acc && !brake) next_state=LOW;else next_state=STOP;LOW:if (brake) next_state=STOP;else if (acc) next_state=MEDIUM;else next_state=LOW;MEDIUM:if (brake) next_state=LOW;else if (acc) next_state=HIGH;else next_state=MEDIUM;HIGH:if (brake) next_state=MEDIUM;else next_state=HIGH;endcase//输出逻辑assign speed=easy ? 2'b01:state;endmodule选项： A:正确; B:错误

6.以下是一个米利型状机 module fsm (input clk,acc,brake,reset, output [1:0] speed ); reg [1:0] state; reg [1:0] next_state; localparam STOP=2'b00; localparam LOW=2'b01; localparam MEDIUM=2'b10; localparam HIGH =2'b11; //状态转换 always@(posedge clk or posedeg reset) if(reset) state=STOP; elsestate=next_state; //次态计算 always@(*) case(state) STOP: if (acc && !brake) next_state=LOW; else next_state=STOP; LOW: if (brake) next_state=STOP; else if (acc) next_state=MEDIUM; else next_state=LOW; MEDIUM: if (brake) next_state=LOW; else if (acc) next_state=HIGH; else next_state=MEDIUM; HIGH: if (brake) next_state=MEDIUM; else next_state=HIGH; endcase //输出逻辑 assign speed=state; endmodule选项： A:正确; B:错误

7."101"序列检测设计三过程描述 ,完成填空！ module fsm_seg101(clk,clr,x,z); input clk, clr,x; output z; reg z; reg[1:0] state,next_state; //状态编码： parameter S0=2'b00, S1=2'b01, S2=2'b11, S3=2'b01; //现态 always @(posedge clk or posedge clr) /*该过程定义当前状态*/ beginif(clr) state<=S0; else state<=next_state; end always @(state or x) /*该过程定义次态*/ begin case ( ① ) S0:begin if(x) next_state<=S1;else next_state<=S0; end S1:beginif(x) next_state<=S1;else next_state<=S2; end S2:beginif(x) next_state<=S3;else next_state<=S0; end S3: begin if(x) next_state<=S1; else next_state<=S2; end default:next_state<=S0; /*default语句*/ endcase end /*该过程产生输出逻辑 OL */ always @(state) /*该过程产生输出逻辑*/ begin case(state) S3: z=1'b1; default:z=1'b0; endcase end endmodule 选项： A、state B、next_state

8.以下代码描述的是:( ).module count(out,data,load,reset,clk);output[7:0] out; input[7:0] data;input load,clk,reset; reg[7:0] out;always @(posedge clk) begin if(!reset) out=8'h00; else if(load) out=data; else out=out+1; endendmodule

9.中国大学MOOC: 下面是一个计数器模块的代码，哪一种说法不正确？module counter (qout, reset, clk);output [3:0] qout;input clk, reset;reg [3:0] qout;always @ (posedge clk) begin if (reset) qout<=0; // else qout<=qout+1; // endendmodule

10.智慧职教: module dff_2（data,clk,reset,q); input data,clk,reset; output q; reg q; always@(posedge clk or negedge reset) begin if(reset==1’b0) q<=1’b0; else q <= data; end endmodule

11.中国大学MOOC: 以下Verilog HDL代码描述的是什么电路？module sr ( input wire clk,si,ld,reset,en, input wire [7:0]d, output reg [7:0]q ); always@(posedge clk, negedge reset) begin if(!reset) q <= 8b0000_0000; else begin if(en) q <= {q[6:0],si}; if(ld) q <= d; end end endmodule

12.4位二进制加法计数器module count4(out,reset,clk);input reset,clk; output reg[3:0] out;A、lways @(posedge clk)B、eginC、if(reset) out<=0; //同步复位D、lse out<=out 1; //计数E、ndF、ndmodule

13.根据程序描述的逻辑功能，下列说法正确的有： module Learn7_1(clk,CLR,LD,out); input clk,CLR,LD,data; output reg[3:0] out; always@(posedge clk or negedge CLR) begin if(!CLR) out<=0; else if(!LD) out<=data; else out<=out+1; end endmodule

14.下面为某可变计数器的Verilog HDL代码，当A=1时，为7进制；当A=0时，为9进制。试补充完空白处代码。 module Alterable_Counter(A, clk, Q); input clk, A; output reg [3:0] Q; parameter N=7; parameter M=9; always @(posedge clk) begin if(A) begin if (__________) begin Q<=0; end else begin Q<=_______; end end else begin if (___________) begin Q<=0; end else begin Q<=Q+1; end end end endmodule

15.74HC161计数器的设计 module hc74161(clk,rst,load,D,Q,out); input clk,rst,load; input [3:0] D; output reg（1） Q; output reg out; always@(posedge clk,（2）rst) begin if(!rst) Q<=0; else begin if(!load) （3）; else begin if(Q==4'b1111) begin out<=1; （4）; end else begin （5）; out<=0; end end end end endmodule