根据程序描述的逻辑功能,下列说法正确的有: module Learn7_1(clk,CLR,LD,out); input clk,CLR,LD,data; output reg[3:0] out; always@(posedge clk or negedge CLR) begin if(!CLR) out<=0; else if(!LD) out<=data; else out<=out+1; end endmodule
发布时间:2024-06-22 23:38:03