选出摩尔型状态机选项： A:module fsm(input clk,acc,brake,reset,output [1:0] spe

2.以下是一个米利型状机 module fsm (input clk,acc,brake,reset, output [1:0] speed ); reg [1:0] state; reg [1:0] next_state; localparam STOP=2'b00; localparam LOW=2'b01; localparam MEDIUM=2'b10; localparam HIGH =2'b11; //状态转换 always@(posedge clk or posedeg reset) if(reset) state=STOP; elsestate=next_state; //次态计算 always@(*) case(state) STOP: if (acc && !brake) next_state=LOW; else next_state=STOP; LOW: if (brake) next_state=STOP; else if (acc) next_state=MEDIUM; else next_state=LOW; MEDIUM: if (brake) next_state=LOW; else if (acc) next_state=HIGH; else next_state=MEDIUM; HIGH: if (brake) next_state=MEDIUM; else next_state=HIGH; endcase //输出逻辑 assign speed=state; endmodule选项： A:正确; B:错误

3.以下是一个米利型状机module fsm(input clk,acc,brake,reset,output [1:0] speed );reg [1:0] state;reg [1:0] next_state;localparam STOP=2'b00;localparam LOW=2'b01;localparam MEDIUM=2'b10;localparam HIGH =2'b11;//状态转换always@(posedge clk or posedeg reset)if(reset) state=STOP;elsestate=next_state;//次态计算always@(*)case(state)STOP:if (acc && !brake) next_state=LOW;else next_state=STOP;LOW:if (brake) next_state=STOP;else if (acc) next_state=MEDIUM;else next_state=LOW;MEDIUM:if (brake) next_state=LOW;else if (acc) next_state=HIGH;else next_state=MEDIUM;HIGH:if (brake) next_state=MEDIUM;else next_state=HIGH;endcase//输出逻辑assign speed=state;endmodule选项： A:正确; B:错误

4.下列Moore型状态机采用Verilog语言主控时序部分正确的是：选项： A、always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B、always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C、always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D、always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;

5.下列Moore型状态机采用Verilog语言主控时序部分正确的是：选项： A:always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end; B:always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end; C:always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state;; D:always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;

6.下列Moore型状态机采用Verilog语言主控时序部分正确的是：选项： A、always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end B、always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end C、always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state; D、always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;

7.请问如下代码中seq1111模块所描述的状态机属于哪一种？ module seq1111(in,clk,clr,out); input in,clk,clr; output out; reg out; parameter s0=3'b000,s1=3'b001,s2=3'b010,s3=3'b110,s4=3'b111; reg [2:0] current_state, next_state; always @(posedge clk) if (clr) current_state<=s0; else current_state<=next_state; always @(*) case(current_state) s0:if (in==1) next_state=s1; else next_state=s0; s1:if (in==1) next_state=s2; else next_state=s0; s2:if (in==1) next_state=s3; else next_state=s0; s3:if (in==1) next_state=s4; else next_state=s0; s4:if (in==1) next_state=s4; else next_state=s0; default:next_state=s0; endcase always @(current_state) if (current_state==s4) out=1; else out=0; endmodule 选项：A、摩尔状态机B、米利状态机

8.已知状态转移图如下：

请在下划线处填写正确的代码：module reduce (clk, reset, in, out); input clk, reset, in; output out; parameter S0 = 2’b00; parameter S1 = 2’b01; parameter S2 = 2’b10; reg out; reg [1:0] state; reg [1:0] next_state; always @(posedge clk) if (reset) state = S0; e lse state = next_state;always @(in or state) case (state) ………… S1: begin if (in) next_state = S2; else next_state = ; end …………

9.阅读下列代码，关于这段代码说法正确的是（）。module fsm_example ( clk, rst_n, datain, result);input clk，rst_n;input datain;output reg result;parameter IDLE = 2'b00;parameter S0 = 2'b01;parameter S1 = 2'b10;reg [1:0] curr_state,reg [1:0] next_state; always@(posedge clk or negedge rst_n) // 第一段begin if (~rst_n) curr_state <= IDLE; else curr_state <= next_state;end always@(*) // 第二段begin case (curr_state) IDLE : if (datain) next_state = S0; else next_state = IDLE; S0 : if (datain) next_state = S1; else next_state = IDLE; S1 : if (datain） next_state = S1; else next_state = IDLE; default : next_state = IDLE; endcaseend always@(*) // 第三段begin case (curr_state) IDLE : result = 1'b0; S0 : result = 1'b0; S1 : result = 1'b1; default : result = 1'b0; endcaseendendmodule 选项： A、这段代码中定义了3个状态：IDLE、S0、S1 B、用于序列检测，当连续输入三个clk周期的高电平时，输出result为高电平 C、第一个always语句块将下一个状态逻辑产生的状态存入curr_state D、第二、三个always语句块均是组合逻辑，前者根据输入和当前状态，产生next_state，后者根据当前状态产生输出

10.阅读下列代码，关于这段代码说法错误的是（）。module fsm_example ( clk, rst_n, datain, result);input clk，rst_n;input datain;output reg result;parameter IDLE = 2'b00;parameter S0 = 2'b01;parameter S1 = 2'b10;reg [1:0] curr_state,reg [1:0] next_state;always@(posedge clk or negedge rst_n) // 第一段begin if (~rst_n) curr_state <= IDLE; else curr_state <= next_state;endalways@(*) // 第二段begin case (curr_state) IDLE : if (datain) next_state = S0; else next_state = IDLE; S0 : if (datain) next_state = S1; else next_state = IDLE; S1 : if (datain） next_state = S1; else next_state = IDLE; default : next_state = IDLE; endcaseendalways@(*) // 第三段begin case (curr_state) IDLE : result = 1'b0; S0 : result = 1'b0; S1 : result = 1'b1; default : result = 1'b0; endcaseendendmodule 选项： A、这段代码中定义了3个状态：IDLE、S0、S1 B、用于序列检测，当连续输入三个clk周期的高电平时，输出result为高电平 C、第一个always语句块将下一个状态逻辑产生的状态存入curr_state D、第二、三个always语句块均是组合逻辑，前者根据输入和当前状态，产生next_state，后者根据当前状态产生输出

11."101"序列检测设计三过程描述 ,完成填空！ module fsm_seg101(clk,clr,x,z); input clk, clr,x; output z; reg z; reg[1:0] state,next_state; //状态编码： parameter S0=2'b00, S1=2'b01, S2=2'b11, S3=2'b01; //现态 always @(posedge clk or posedge clr) /*该过程定义当前状态*/ beginif(clr) state<=S0; else state<=next_state; end always @(state or x) /*该过程定义次态*/ begin case ( ① ) S0:begin if(x) next_state<=S1;else next_state<=S0; end S1:beginif(x) next_state<=S1;else next_state<=S2; end S2:beginif(x) next_state<=S3;else next_state<=S0; end S3: begin if(x) next_state<=S1; else next_state<=S2; end default:next_state<=S0; /*default语句*/ endcase end /*该过程产生输出逻辑 OL */ always @(state) /*该过程产生输出逻辑*/ begin case(state) S3: z=1'b1; default:z=1'b0; endcase end endmodule 选项： A、state B、next_state

12.有关下列代码说法正确的是()always @(posedge clk,posedge reset)beginif (reset)current_state =S0;elsecurrent_state =next_state;end

13.选出正确的带复位控制的触发器选项： A:module D_FF ( input D,Clock,reset, output reg Q); always@(Posedge Clock or reset) if ( reset==1) Q <=0; else Q <=D; endmodule; B:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or posedge reset) if ( reset==1) Q <=0; else Q <=D; endmodule; C:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or negedge reset) if ( reset==1) Q <=0; else Q <=D; endmodule; D:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or posedeg reset) if ( reset==0) Q <=0; else Q <=D; endmodule; E:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or reset) if ( reset==1) Q <=0; else Q <=D; endmodule; F:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or reset) if ( reset==0) Q <=0; else Q <=D; endmodule; G:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock) if ( reset==1) Q <=0; else Q <=D; endmodule

14.选出右移移位寄存器选项： A:module Shifter ( input Dsi, input CLK, output reg [3:0] Q); always@(posedeg clk) begin Q[3]<= Dsi; Q[2]<=Q[3]; Q[1]<=Q[2]; Q[0]<=Q[1];end endmodule; B:module Shifter ( input Dsi, input CLK, output reg [3:0] Q); always@(posedeg clk) begin Q[3]<=Q[2]; Q[2]<=Q[1]; Q[1]<=Q[0]; Q[0]<=Dsi; end endmodule; C:module Shifter ( input Dsi, input CLK, output reg [0:3] Q); always@(posedeg clk) begin Q[0]<= Dsi; Q[1]<=Q[0]; Q[2]<=Q[1]; Q[3]<=Q[2]; end endmodule; D:module Shifter ( input Dsi, input CLK, output reg [0:3] Q); always@(posedeg clk) Q[0:3]<={ Dsi,Q[0:2]};endmodule; E:module Shifter ( input Dsi, input CLK, output reg [0:3] Q); always@(posedeg clk) Q[0:3]<={Q[1:3],Dsi};endmodule; F:module Shifter (input Dsi, input [3:0] In, input CLK, output reg [3:0] Q); always@(posedeg clk) if(Load) Q<= In; else Q<={Dsi,Q[3:1]};endmodule; G:module Shifter (input Dsi, input CLK,reset, output reg [3:0] Q); always@(posedge clk or posedge reset) if(reset) Q<= 4'b1000;else Q<={Q[2:0],Q[3]}; end module

15.选出16分频计数器选项： A:module counter ( input Clock,Reset, output clkout); reg [7:0] Q; always@(posedge Clock,posedge Reset) if(Reset==1) Q<=0; else Q<=Q+1; assign clkout<=Q[3]; endmodule; B:module counter ( input Clock,Reset, output reg clkout); reg [7:0] Q; always@(posedge Clock,posedge Reset) if(Reset==1) begin Q<=0; clkout<=0; end else if (Q==16) begin clkout<=~clkout; Q<=0; end else Q<=Q+1; endmodule; C:module counter ( input Clock,Reset, output reg clkout); reg [7:0] Q; always@(posedge Clock,posedge Reset) if(Reset==1) begin Q<=0; clkout<=0; end else if (Q==8) begin clkout<=~clkout; Q<=0; end else Q<=Q+1; endmodule; D:module counter ( input Clock,Reset, output reg clkout); reg [7:0] Q; always@(posedge Clock,posedge Reset) if(Reset==1) begin Q<=0; clkout<=0; end else if (Q==7) begin clkout<=~clkout; Q<=0; end else Q<=Q+1; endmodule

16.选出正确的带复位控制的触发器选项： A:module D_FF ( input D,Clock,reset, output reg Q); always@(Posedge Clock or reset) if ( reset==1) Q <=0; else Q <=D; endmodule; B:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or posedge reset) if ( reset==1) Q <=0; else Q <=D; endmodule; C:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or negedge reset) if ( reset==1) Q <=0; else Q <=D; endmodule; D:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or posedeg reset) if ( reset==0) Q <=0; else Q <=D; endmodule; E:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or reset) if ( reset==1) Q <=0; else Q <=D; endmodule; F:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or reset) if ( reset==0) Q <=0; else Q <=D; endmodule; G:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock) if ( reset==1) Q <=0; else Q <=D; endmodule

17.选出正确的带复位控制的触发器选项： A:module D_FF ( input D,Clock,reset, output reg Q); always@(Posedge Clock or reset) if ( reset==1) Q <=0; else Q <=D; endmodule; B:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or posedge reset) if ( reset==1) Q <=0; else Q <=D; endmodule; C:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or negedge reset) if ( reset==1) Q <=0; else Q <=D; endmodule; D:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or posedeg reset) if ( reset==0) Q <=0; else Q <=D; endmodule; E:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock or reset) if ( reset==1) Q <=0; else Q <=D; endmodule; F:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock) if ( reset==0) Q <=0; else Q <=D; endmodule; G:module D_FF ( input D,Clock,reset, output reg Q); always@(posedge Clock) if ( reset==1) Q <=0; else Q <=D; endmodule

18.选出右移移位寄存器选项： A:module Shifter( input Dsi,input CLK,output reg [3:0] Q);always@(posedeg clk) begin Q[3]<= Dsi; Q[2]<=Q[3]; Q[1]<=Q[2]; Q[0]<=Q[1];end endmodule; B:module Shifter( input Dsi,input CLK,output reg [3:0] Q);always@(posedeg clk) begin Q[3]<=Q[2]; Q[2]<=Q[1]; Q[1]<=Q[0]; Q[0]<=Dsi; end endmodule; C:module Shifter( input Dsi,input CLK,output reg [0:3] Q);always@(posedeg clk)begin Q[0]<= Dsi; Q[1]<=Q[0]; Q[2]<=Q[1]; Q[3]<=Q[2]; end endmodule; D:module Shifter( input Dsi,input CLK,output reg [0:3] Q);always@(posedeg clk) Q[0:3]<={ Dsi,Q[0:2]};endmodule; E:module Shifter( input Dsi,input CLK,output reg [0:3] Q);always@(posedeg clk) Q[0:3]<={Q[1:3],Dsi};endmodule; F:module Shifter(input Dsi,input [3:0] In,input CLK,output reg [3:0] Q);always@(posedeg clk) if(Load) Q<= In; else Q<={Dsi,Q[3:1]};endmodule; G:module Shifter(input Dsi,input CLK,reset,output reg [3:0] Q);always@(posedge clk or posedge reset) if(reset) Q<= 4'b1000;else Q<={Q[2:0],Q[3]}; end module

19.有关下列代码说法正确的是（）always @ (posedge clk, posedge reset) beginif (reset)current_state = S0; elsecurrent_state = next_state;end 选项： A、复位功能是同步的 B、always块是在时钟高电平时触发 C、该段代码为状态寄存器，实现状态的迭代 D、系统的初始状态未知

20.以下程序描述的电路结构,包含哪些元件？module test8(CLK,D,Q,RESET,EN,SET);input CLK,D,RESET,EN,SET;output Q;reg Q;wire PRE;assign PRE=SET & RESET;always@(posedge CLK or negedge RESET or posedge SET)begin if (!RESET) Q<=0;else if (SET) Q<=1;else if (EN) Q<=D;endendmodule选项： A:锁存器; B:D触发器; C:与门; D:或门

21.以下程序描述的电路结构,包含哪些元件？module test8(CLK,D,Q,RESET,EN,SET);input CLK,D,RESET,EN,SET;output Q;reg Q;wire PRE;assign PRE=SET & RESET;always@(posedge CLK or negedge RESET or posedge SET)begin if (!RESET) Q<=0;else if (SET) Q<=1;else if (EN) Q<=D;endendmodule 选项： A、锁存器 B、D触发器 C、与门 D、或门

22.已知时钟信号clkin的频率为100MHz的方波信号，clkout信号的占空比为？module function(rst, clkin, clkout);input clkin, rst;output wire clkout;reg[2:0] m, n;reg clk1, clk2;assign clkout=clk1|clk2; always @(posedge clkin)begin if(!rst) begin clk1<=0; m<=0; end else begin if(m==4) m<=0; else m<=m+1; if(m<2) clk1<=1; else clk1<=0; endend always @(negedge clkin)begin if(!rst) begin clk2<=0; n=0; end else begin if(n==4) n<=0; else n<=n+1; if(n<2) clk2<=1; else clk2<=0; endendendmodule 选项： A、10% B、20% C、40%Hz D、50%

23.【单选题】某设计的VerilogHDL程序如下,该设计描述的计数器的模是() module my_counter(input reset,clk,output reg[3:0] out); always@(posedge clk) Begin if(reset) out=0; else out=out+1; end endmodule 选项： A、4 B、8 C、16 D、32

24.选出具有使能控制的触发器或寄存器的正确描述。选项： A:module D_ff ( input D,CLK,En, output reg Q ); always@(posedge CLK) begin if (En) Q <= D; end endmodule; B:module D_ff ( input D,CLK,En, output reg Q ); always@(posedge CLK or posedge En) begin if (En) Q <=0; else Q =D; endendmodule; C:module D_ff ( input D,CLK, output reg Q ); always@(posedge CLK) begin Q <= D; end endmodule; D:module D_ff ( input D,CLK,En, output reg Q ); wire gateclk; assign gateclk=(En&CLK); always@(posedge GATECLK) begin if (En) Q < =D; end endmodule; E:module D_ff ( input CLK,load, input [3:0] D, output reg [3:0] Q ); always@(posedeg CLK) begin if (load) Q <= D; end endmodule