下列Moore型状态机采用Verilog语言主控时序部分正确的是:
选项:
A:always@(posedge clk or negedge reset) begin if(!reset) current_state<=s0; else current_state<=next_state; end
B:always@(posedge clk ) begin if(!reset) current_state<=s0; else current_state<=next_state; end
C:always@(posedge clk t) if(reset) current_state<=s0; else current_state<=next_state;
D:always@(posedge clk or negedge reset) if(reset) current_state<=s0; else current_state<=next_state;
发布时间:2024-04-21 21:06:49