下列程序中。module counter1( out, cout, data, load, cin, clk);output [7:0] out;output cout;input [7:0] data;input load, cin, clk;reg [7:0] out;always @(posedge clk)beginif( load )out = data;elseout = out + cin;endassign cout= out & cin;endmoudle
选项：

A:cout为向高位的进位, data为低位的进位, load是计数脉冲
B: cout为低位的进位, data 数据输入, clk是计数脉冲
C: cout是高位进位, cin是低位进位, clk是计数脉冲
D: cout是数据输出, cin是数据输入, clk置数据控制