下列描述中采用时钟clk正边沿触发且rst异步低电平复位的代码描述是选项: A:always @ (posedge clk, negedge rst)if (rst); B:always @ (posedge clk, rst)if (!rst); C:always @ (posedge clk, negedge rst)if (!rst); D:always @ (negedge clk, posedge rst)if (rst) 采用 代码 发布时间:2024-05-17 11:41:27