接上题,要实现该分频电路的功能,则(1)应为( )。module div_1s(clk,clkout);input clk;output reg clkout;reg [23:0] cnt;always@(posedge clk)begin if(cnt== 24'd5999_999 ) (1) ; else cnt<=cnt+1'b1;endalways@(posedge clk)begin if(cnt== (2) ) (3) ; else;endendmodule;
选项:
A:cnt<=0;;
B:clkout<=1'b0;;
C:cnt<=1'b1;;
D:cnt<=24'd5999999;
发布时间:2024-05-17 20:02:42