阅读下列代码,关于这段代码说法错误的是( )。module fsm_example ( clk, rst_n, datain, result);input clk,rst_n;input datain;output reg result;parameter IDLE = 2'b00;parameter S0 = 2'b01;parameter S1 = 2'b10;reg [1:0] curr_state,reg [1:0] next_state;always@(posedge clk or negedge rst_n) // 第一段begin if (~rst_n) curr_state <= IDLE; else curr_state <= next_state;endalways@(*) // 第二段begin case (curr_state) IDLE : if (datain) next_state = S0; else next_state = IDLE; S0 : if (datain) next_state = S1; else next_state = IDLE; S1 : if (datain) next_state = S1; else next_state = IDLE; default : next_state = IDLE; endcaseendalways@(*) // 第三段begin case (curr_state) IDLE : result = 1'b0; S0 : result = 1'b0; S1 : result = 1'b1; default : result = 1'b0; endcaseendendmodule
选项:
A:这段代码中定义了3个状态:IDL
E:S0、S1
B:用于序列检测,当连续输入三个clk周期的高电平时,输出result为高电平
C:第一个always语句块将下一个状态逻辑产生的状态存入curr_state
D:第二、三个always语句块均是组合逻辑,前者根据输入和当前状态,产生next_state,后者根据当前状态产生输出
发布时间:2024-04-21 21:06:49